By Patricia J. Teller (auth.), Michel Dubois, Shreekant S. Thakkar (eds.)
Cache And Interconnect Architectures In Multiprocessors Eilat, Israel could 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems the purpose of the workshop was once to assemble researchers engaged on cache coherence protocols for shared-memory multiprocessors with a number of interconnect architectures. Shared-memory multiprocessors became practicable structures for plenty of purposes. Bus established shared-memory structures (Eg. Sequent's Symmetry, Encore's Multimax) are at present restricted to 32 processors. the 1st aim of the workshop used to be to benefit in regards to the functionality ofapplications on present cache-based structures. the second one aim used to be to profit approximately new community architectures and protocols for destiny scalable structures. those protocols and interconnects might permit shared-memory architectures to scale past present imitations. The workshop had 20 audio system who referred to their present examine. The discussions have been full of life and cordial adequate to maintain the contributors clear of the glorious sand and sunlight for 2 days. The individuals bought to understand one another good and have been in a position to proportion their innovations in a casual demeanour. The workshop used to be geared up into a number of periods. The precis of every consultation is defined under. This publication offers revisions of a few of the papers offered on the workshop.
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Extra resources for Cache and Interconnect Architectures in Multiprocessors
1 Overview A processor simulator that represents the execution of actual program code, instruction by instruction, holds intuitive justification. However, such a simulator is expensive to build and slow to run, so trace-driven simulation is often adopted for uniprocessors where possible. Trace-driven simulation (TDS) holds intuitive validity if the trace represents a sequence of instructions and memory references that is independent of the architecture being evaluated; that is, the sequence depends only on its internal consistency.
5 Support For Memory Management Although each process has its own page tables for virtual-to-physical address translation, there are many cases where a page table entry (noted PTE) can be shared by different processors. For example, in UNIX System V, when a parent process "forks" a child process, the resulting processes share access to the page table for the shared text region . IT the child process is scheduled on a separate processor, multiple copies of the information contained in a PTE are cached in distinct TLBs and possibly cache tags.
The consequence is that under ATDS trace B executes an unnecessary delay (because it was necessary during original execution). The figure also shows that mutual exclusion may be violated, access to trace A being incorrectly allowed (because it was correctly allowed during original execution). Finally, the figure also shows that the action that follows from the access protected by test-and-set is the action that was appropriate during original execution, in which trace A made its protected access before trace B made its protected access.